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X5001
CPU Supervisor
Features * 200ms Power On Reset Delay * Low Vcc Detection and Reset Assertion --Five Standard Reset Threshold Voltages --Adjust Low Vcc Reset Threshold Voltage using special programming sequence --Reset Signal Valid to Vcc=1V * Selectable Nonvolatile Watchdog Timer --0.2, 0.6, 1.4 seconds --Off selection --Select settings through software * Long Battery Life With Low Power Consumption --<50A Max Standby Current, Watchdog On --<1A Max Standby Current, Watchdog Off * 2.7V to 5.5V Operation * SPI Mode 0 interface * Built-in Inadvertent Write Protection --Power-Up/Power-Down Protection Circuitry --Watchdog Change Latch * High Reliability * Available Packages --8-Lead TSSOP --8-Lead SOIC --8 Pin PDIP DESCRIPTION This device combines three popular functions, Power on Reset, Watchdog Timer, and Supply Voltage Supervision in one package. This combination lowers system cost, reduces board space requirements, and increases reliability. The Watchdog Timer provides an independent protection mechanism for microcontrollers. During a system failure, the device will respond with a RESET signal after a selectable time-out interval. The user selects the interval from three preset values. Once selected, the interval does not change, even after cycling the power. The user's system is protected from low voltage conditions by the device's low Vcc detection circuitry. When Vcc falls below the minimum Vcc trip point, the system is reset. RESET is asserted until Vcc returns to proper operating levels and stabilizes. Five industry standard VTRIP thresholds are available, however, Xicor's unique circuits allow the thresold to be reprogrammed to meet custom requirements or to fine-tune the threshold for applications requiring higher precision. The device utilizes Xicor's proprietary Direct WriteTM cell for the Watchdog TImer control bits and the VTRIP storage element, providing a minimum endurance of 100,000 write cycles and a minimum data retention of 100 years.
Block Diagram
RESET
WATCHDOG TRANSITION DETECTOR
WATCHDOG TIMER
SI SO SCK CS/WDI
DATA REGISTER COMMAND DECODE & CONTROL LOGIC POWER ON/ LOW VOLTAGE RESET
+
RESET & WATCHDOG TIMEBASE
VCC
VTRIP
GENERATION
-
7036 FRM 01 (c)Xicor, Inc. 1994, 1995, 1996, 1998 Patents Pending 7078 1.1 8/9/99 CM
1
Characteristics subject to change without notice
X5001
PIN DESCRIPTION
PIN (SOIC/PDIP) PIN TSSOP Name Function
1
1
CS/WDI
Chip Select Input. CS HIGH, deselects the device and the SO output pin is at a high impedance state. Unless a nonvolatile write cycle is underway, the device will be in the standby power mode. CS LOW enables the device, placing it in the active power mode. Prior to the start of any operation after power up, a HIGH to LOW transition on CS is required Watchdog Input. A HIGH to LOW transition on the WDI pin restarts the Watchdog timer. The absence of a HIGH to LOW transition within the watchdog timeout period results in RESET/RESET going active. Serial Output. SO is a push/pull serial data output pin. A read cycle shifts data out on this pin. The falling edge of the serial clock (SCK) clocks the data out. Serial Input. SI is a serial data input pin. Input all opcodes, byte addresses, and memory data on this pin. The rising edge of the serial clock (SCK) latches the input data. Send all opcodes (Table 1), addresses and data MSB first. Serial Clock. The Serial Clock controls the serial bus timing for data input and output. The rising edge of SCK latches in the opcode, address, or watchdog bits present on the SI pin. The falling edge of SCK changes the data output on the SO pin. VTRIP Program Enable. When VPE is LOW, the VTRIP point is fixed at the last valid programmed level. To readjust the VTRIP level, requires that the VPE pin be pulled to a high voltage (15-18V). Ground Supply Voltage Reset Output. RESET is an active LOW, open drain output which goes active whenever Vcc falls below the minimum Vcc sense level. It will remain active until Vcc rises above the minimum Vcc sense level for 200ms. RESET goes active if the Watchdog Timer is enabled and CS/WDI remains either HIGH or LOW longer than the selectable Watchdog time-out period. A falling edge of CS/WDI will reset the Watchdog Timer. RESET goes active on power up at 1V and remains active for 200ms after the power supply stabilizes. No internal connections
2 5
2 8
SO SI
6
9
SCK
3 4 8
6 7 14
VPE VSS VCC
7
13
RESET
3-5,10-12
NC
Figure 1. PIN CONFIGURATION
8 Lead TSSOP RESET
VCC
8 Lead SOIC/PDIP SCK SI V SS VPE CS/WDI SO VPE VSS 1 X5001 2 3 4 8 7 6 5 V CC RESET SCK SI
1 3 4 X5001 2
8 7 6 5
CS/WDI SO
2
X5001
PRINCIPLES OF OPERATION Power On Reset Application of power to the X5001 activates a Power On Reset Circuit. This circuit goes active at 1V and pulls the RESET/RESET pin active. This signal prevents the system microprocessor from starting to operate with insufficient voltage or prior to stabilization of the oscillator. When Vcc exceeds the device VTRIP value for 200ms (nominal) the circuit releases RESET, allowing the processor to begin executing code. Low voltage monitoring During operation, the X5001 monitors the VCC level and asserts RESET if supply voltage falls below a preset minimum VTRIP. The RESET signal prevents the microprocessor from operating in a power fail or brownout condition. The RESET signal remains active until the voltage drops below 1V. It also remains active until Vcc returns and exceeds VTRIP for 200ms. watchdog timer The Watchdog Timer circuit monitors the microprocessor activity by monitoring the WDI input. The microprocessor must toggle the CS/WDI pin periodically to prevent a RESET signal. The CS/WDI pin must be toggled from HIGH to LOW prior to the expiration of the watchdog timeout period. The state of two nonvolatile control bits in the Watchdog Register determine the watchdog timer period. Vcc Threshold Reset Procedure The X5001 is shipped with a standard Vcc threshold (VTRIP) voltage. This value will not change over normal operating and storage conditions. However, in applications where the standard VTRIP is not exactly right, or if higher precision is needed in the VTRIP value, the X5001 threshold may be adjusted. The procedure is described below, and requires the application of a high voltage control signal. Setting the VTRIP Voltage This procedure is used to set the VTRIP to a higher voltage value. For example, if the current VTRIP is 4.4V and the new VTRIP is 4.6V, this procedure will directly make the change. If the new setting is to be lower than the current setting, then it is necessary to reset the trip point before setting the new value.
To set the new VTRIP voltage, apply the desired VTRIP threshold voltage to the Vcc pin and tie the WPE pin to the programming voltage VP. Then a VTRIP programming command sequence is sent to the device over the SPI interface. This VTRIP programming sequence consists of pulling CS LOW, then clocking in data 03h, 00h and 01h. This is followed by bringing CS HIGH then LOW and clocking in data 02h, 00h, and 01h (in order) and bringing CS HIGH. This initiates the VTRIP programming sequence. VP is brought LOW to end the operation. Resetting the VTRIP Voltage This procedure is used to set the VTRIP to a "native" voltage level. For example, if the current VTRIP is 4.4V and the new VTRIP must be 4.0V, then the VTRIP must be reset. When VTRIP is reset, the new VTRIP is something less than 1.7V. This procedure must be used to set the voltage to a lower value. To reset the VTRIP voltage, apply greater than 3V to the Vcc pin and tie the WPE pin to the programming voltage Vp. Then a VTRIP command sequence is sent to the device over the SPI interface. This VTRIP programming sequence consists of pulling CS LOW, then clocking in data 03h, 00h and 01h. This is followed by bringing CS HIGH then LOW and clocking in data 02h, 00h, and 03h (in order) and bringing CS HIGH. This initiates the VTRIP programming sequence. VP is brought LOW to end the operation.
3
X5001
Figure 2. Sample VTRIP Reset Circuit 4.7K Adjust VTRIP Adj. Run
1 2 3 4 X5001 8 7 6 5
VP
RESET SCK SI SO CS
uC
Figure 3. Set VTRIP Level Sequence (Vcc=desired VTRIP value. ) VPE = 15-18V
VPE
CS
0 1 2 3 4 5 6 7 8 9 10
SCK
20 21 22 23
0 1 2 3 4 5 6 7 8 9 10
20 21 22 23
16 BITS
SI
16 BITS
03h
0001h
02h
0001h
Figure 4. Reset VTRIP Level Sequence (Vcc > 3V. )
VPE
VPE = 15-18V
CS
0 1 2 3 4 5 6 7 8 9 10
SCK
20 21 22 23
0 1 2 3 4 5 6 7 8 9 10
20 21 22 23
16 BITS
SI
16 BITS
03h
0001h
02h
0003h
4
X5001
Figure 5. Vtrip Programming Sequence
Vtrip Programming
Execute Reset Vtrip Sequence
Set Vcc = Vcc applied = Desired Vtrip
New Vcc applied = Old Vcc applied + Error
Execute Set Vtrip Sequence
New Vcc applied = Old Vcc applied - Error
Apply 5V to Vcc
Execute Reset Vtrip Sequence
Decrement Vcc (Vcc = Vcc - 50mV)
NO
RESET pin goes active?
YES
Error < 0
Measured Vtrip Desired Vtrip
Error > 0
Error = 0
DONE
5
X5001
spi Interface The device is designed to interface directly with the synchronous Serial Peripheral Interface (SPI) of many popular microcontroller families. The device monitors the CS/WDI line and asserts RESET output if there is no activity within user selctable time-out period. The device also monitors the Vcc supply and asserts the RESET if Vcc falls below a preset minimum (VTRIP). The device contains an 8-bit Watchdog Timer Register to control the watchdog time-out period. The current settings are accessed via the SI and SO pins. All instructions (Table 1) and data are transferred MSB first. Data input on the SI line is latched on the first rising edge of SCK after CS goes LOW. Data is output on the SO line by the falling edge of SCK. SCK is static, allowing the user to stop the clock and then start it again to resume operations where left off. Watchdog Timer Register 7
0
Watchdog Change Latch The Watchdog Change Latch must be SET before a Write Watchdog Timer Operation is initiated. The Enable Watchdog Change (EWDC) instruction will set the latch and the Disable Watchdog Change (DWDC) instruction will reset the latch (See Figure 2.) This latch is automatically reset upon a power-up condition and after the completion of a valid nonvolatile write cycle. Read Watchdog Timer Register Operation If there is not a nonvolatile write in progress, the Read Watchdog Timer instruction returns the setting of the watchdog timer control bits. The other bits are reserved and will return '0' when read. See Figure 3. If a nonvolatile write is in progress, the Read Watchdog Timer Register Instruction returns a HIGH on SO. When the nonvolatile write cycle is completed, a seperate Read Watchdog Timer instruction should be used to determine the current status of the Watchdog control bits. RESET Operation The RESET (X5001) output is designed to go LOW whenever VCC has dropped below the minimum trip point and/or the Watchdog timer has reached its programmable time-out limit. The RESET output is an open drain output and requires a pull up resistor. Operational Notes The device powers-up in the following state: * The device is in the low power standby state. * A HIGH to LOW transition on CS is required to enter an active state and receive an instruction. * SO pin is high impedance. * The Watchdog Change Latch is reset. * The RESET Signal is active for tPURST. Data Protection The following circuitry has been included to prevent inadvertent writes: * A EWDC instruction must be issued to enable a change to the watchdog timeout setting. * CS must come HIGH at the proper clock count in order to implement the requested changes to the watchdog timeout setting.
6
0
5
0
4
WD1
3
WD0
2
0
1
0
0
0
Watchdog Timer Control Bits The Watchdog Timer Control bits, WD0 and WD1, select the Watchdog Time-out Period. These nonvolatile bits are programmed with the Set Watchdog Timer (SWDT) instruction. Watchdog Control Bits WD1
0 0 1 1
WD0
0 1 0 1
Watchdog Time-out (Typical)
1.4 Seconds 600 Milliseconds 200 Milliseconds Disabled
Write Watchdog Register Operation Changing the Watchdog Timer Register is a two step process. First, the change must be enabled with by setting the Watchdog Change Latch (see below). This instruction is followed by the Set Watchdog Timer (SWDT) instruction, which includes the data to be written (Figure 5). Data bits 3 and 4 contain the Watchdog settings and data bits 0, 1, 2, 5, 6 and 7 must be "0" .
6
X5001
Table 1. Instruction Set Definition Instruction Format
0000 0110 0000 0100 0000 0001
Instruction Name and Operation
EWDC: Enable Watchdog Change Operation DWDC: Disable Watchdog Change Operation SWDT: Set Watchdog Timer control bits: Instruction followed by contents of register: 000(WD1) (WD0)000 See Watchdog Timer Settings and Figure 3. RWDT: Read Watchdog Timer control bits
0000 0101
Notes: Instructions are shown with MSB in leftmost position. Instructions are transferred MSB first.
7038 FRM T03
Figure 1. Read Watchdog Timer setting
CS
0 SCK
1
2
3
4
5
6
7
... ...
W D 1 W D 0
RWDT INSTRUCTION SI
SO
...
Figure 2. Enable Watchdog Change/Disable Watchdog Change Sequence
CS
0 SCK
1
2
3
4
5
6
7
INSTRUCTION (1 BYTE) SI
SO
HIGH IMPEDANCE
7
X5001
Figure 3. Write Watchdog Timer Sequence
CS 0 SCK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
INSTRUCTION SI 6 5
DATA BYTE 4 W D 1 3 W D 0
SO
HIGH IMPEDANCE
Figure 4. Read Nonvolatile Status (Option 1) (Used to determine end of Watchdog Timer store operation)
CS
0 SCK
1
2
3
4
5
6
7
RWDT INSTRUCTION SI NONVOLATILE WRITE IN PROGRESS
SO
SO HIGH During 1st bit while in the Nonvolatile write cycle
Figure 5. Read Nonvolatile Status (Option 2) (Used to determine end of Watchdog Timer store operation)
CS
0 SCK
1
2
3
4
5
6
7
RWDT INSTRUCTION SI NONVOLATILE WRITE IN PROGRESS
SO SO HIGH During Nonvolatile write cycle
8
X5001
ABSOLUTE MAXIMUM RATINGS* Temperature under Bias ........................-65C to +135C Storage Temperature .............................-65C to +150C Voltage on any Pin with Respect to VSS....... -1.0V to +7V D.C. Output Current ....................................................5mA Lead Temperature (Soldering, 10 seconds)............ 300C RECOMMENDED OPERATING CONDITIONS Temp
Commercial
*COMMENT Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and the functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Voltage Option
-1.8 -2.7 or -2.7A -4.5 or -4.5A
PT= Package, Temperature
Min.
0C
Max.
+70C
7036 FRM T07
Supply Voltage Limits
1.8V to 3.6V 2.7V to 5.5V 4.5V to 5.5V
D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.)
Limits Symbol ICC1 ICC2 ISB1 ISB2 ISB3 ILI ILO VIL(1) VIH VOL1 VOL2 VOL3 VOH1 VOH2 VOH3 VOLRS
(1)
Parameter VCC Write Current (Active) VCC Read Current (Active) VCC Standby Current WDT=OFF VCC Standby Current WDT=ON VCC Standby Current WDT=ON Input Leakage Current Output Leakage Current Input LOW Voltage Input HIGH Voltage Output LOW Voltage Output LOW Voltage Output LOW Voltage Output HIGH Voltage Output HIGH Voltage Output HIGH Voltage Reset Output LOW Voltage
Min.
Typ.
Max. 5 0.4 1 50 20
Units mA mA A A A A A V V V V V V V V
Test Conditions SCK = VCC x 0.1/VCC x 0.9 @ 5MHz, SO = Open SCK = VCC x 0.1/VCC x 0.9 @ 5MHz, SO = Open CS = VCC, VIN = VSS or VCC, VCC = 5.5V CS = VCC, VIN = VSS or VCC, VCC = 5.5V CS = VCC, VIN = VSS or VCC, VCC =3.6V VIN = VSS to VCC VOUT = VSS to VCC
0.1 0.1 -0.5 VCCx0.7
10 10 VCCx0.3 VCC+0.5 0.4 0.4 0.4
VCC > 3.3V, IOL = 2.1mA 2V < VCC < 3.3V, IOL = 1mA VCC 2V, IOL = 0.5mA VCC > 3.3V, IOH = -1.0mA VCC 2V, IOH = -0.25mA IOL = 1mA 2V < VCC 3.3V, IOH = -0.4mA
VCC-0.8 VCC-0.4 VCC-0.2 0.4
V
POWER-UP TIMING Symbol
tPUR
(2) (2)
tPUW
Parameter Power-up to Read Operation Power-up to Write Operation
Min.
Max.
1 5
Units
ms ms
CAPACITANCE TA = +25C, f = 1MHz, VCC = 5V. Symbol
COUT CIN
Notes:
(2) (2)
Test Output Capacitance (SO, RESET) Input Capacitance (SCK, SI, CS)
Max.
8 6
Units
pF pF
Conditions
VOUT = 0V VIN = 0V
(1) VIL min. and VIH max. are for reference only and are not tested. (2) This parameter is periodically sampled and not 100% tested. 9
X5001
Figure 1. EQUIVALENT A.C. LOAD CIRCUIT
3V 5V 3.3K
A.C. TEST CONDITIONS Input Pulse Levels Input Rise and Fall Times Input and Output Timing Level VCC x 0.1 to VCC x 0.9 10ns VCC x0.5
1.64K OUTPUT 1.64K 100pF RESET
30pF
A.C. CHARACTERISTICS (Over recommended operating conditions, unless otherwise specified) Data Input Timing 1.8V-3.6V Symbol fSCK tCYC tLEAD tLAG tWH tWL tSU tH tRI
(3)
2.7V-5.5V Min.
0 500 200 200 200 200 50 50 2 2 2 2 150 10 10
Parameter Clock Frequency Cycle Time CS Lead Time CS Lag Time Clock HIGH Time Clock LOW Time Data Setup Time Data Hold Time Input Rise Time Input Fall Time CS Deselect Time Write Cycle Time
Min.
0 1000 400 400 400 400 100 100
Max.
1
Max.
2
Units
MHz ns ns ns ns ns ns ns s s ns ms
tFI(3) tCS tWC(4)
250
Data Output Timing 1.8V-3.6V Symbol fSCK tDIS tV tHO tRO(3) tFO(3)
Notes:
2.7V-5.5V Min.
0
Parameter Clock Frequency Output Disable Time Output Valid from Clock Low Output Hold Time Output Rise Time Output Fall Time
Min.
0
Max.
1 400 400
Max.
2 200 200
Units
MHz ns ns ns
0 300 300
0 150 150
ns ns
(3) This parameter is periodically sampled and not 100% tested. (4) tWC is the time from the rising edge of CS after a valid write sequence has been sent to the end of the self-timed internal nonvolatile write cycle. 10
X5001
Figure 1. Data Output Timing
CS t CYC SCK tV SO MSB OUT MSB-1 OUT tHO t WL LSB OUT tDIS tWH t LAG
SI
ADDR LSB IN
Figure 2. Data Input Timing
tCS CS tLEAD SCK tSU SI MSB IN tH tRI t FI LSB IN tLAG
SO
HIGH IMPEDANCE
Figure 1. Symbol Table
WAVEFORM INPUTS Must be steady May change from LOW to HIGH May change from HIGH to LOW Don't Care: Changes Allowed N/A OUTPUTS Will be steady Will change from LOW to HIGH Will change from HIGH to LOW Changing: State Not Known Center Line is High Impedance
11
X5001
Figure 1. Power-Up and Power-Down Timing
VCC
VTRIP 0 Volts tR
tPURST tPURST
V TRIP tF
tRPD
RESET (X5001)
RESET Output Timing Symbol Parameter
Reset Trip Point Voltage, X5001PT-4.5A Reset Trip Point Voltage, X5001PT-4.5 Reset Trip Point Voltage, X5001PT-2.7A Reset Trip Point Voltage, X5001PT-2.7 Reset Trip Point Voltage, X5001PT-1.8 Power-up Reset Timeout VCC Detect to Reset/Output VCC Fall Time VCC Rise Time Reset Valid VCC
0.1 0.1 1
Min.
4.50 4.25 2.85 2.55 1.70
100
Typ.
4.63 4.38 2.92 2.63 1.75 200
Max.
4.75 4.50 3.00 2.70 1.80
280 500
Units
V
VTRIP
tPURST tRPD tF(5) tR
(5) (5)
ms ns ns ns V
VRVALID
Notes:
(5) This parameter is periodically sampled and not 100% tested. PT = Package, Temperature
Figure 2. CS vs. RESET Timing
CS t CST RESET t WDO tRST tWDO t RST
RESET Output Timing Symbol
tWDO
Parameter
Watchdog Timeout Period, WD1 = 1, WD0 = 0 WD1 = 0, WD0 = 1 WD1 = 0, WD0 = 0 CS Pulse Width to Reset the Watchdog Reset Timeout
Min.
100 450 1 400 100
Typ.
200 600 1.4
Max.
300 800 2
Units
ms ms sec ns
tCST tRST
200
300
ms
12
X5001
VTRIP Programming Timing Diagram
Vcc (VTRIP)
VTRIP
tTSU tTHD
VP
VPE
tVPS
tPCS
tVPH
tVPO
CS
tRP
SCK
SI 03h 0001h 02h 0001h or 0003h
13
X5001
VTRIP Programming Parameters
Parameter Description Min Max Units
tVPS tVPH tPCS tTSU tTHD tWC tVPO tRP VP VTRAN Vta1
VTRIP Program Enable Voltage Setup time VTRIP Program Enable Voltage Hold time VTRIP Programming CS inactive time VTRIP Setup time VTRIP Hold (stable) time VTRIP Write Cycle Time VTRIP Program Enable Voltage Off time (Between successive adjustments) VTRIP Program Recovery Period (Between successive adjustments) Programming Voltage VTRIP Programmed Voltage Range Initial VTRIP Program Voltage accuracy (Vcc applied - VTRIP) (Programmed at 25oC.) Subsequent VTRIP Program Voltage accuracy [(Vcc applied - Vta1) - VTRIP. Programmed at 25oC.) VTRIP Program Voltage repeatability (Successive program operations. Programmed at 25oC.) VTRIP Program variation after programming (0-75oC). (Programmed at 25oC.)
1 1 1 1 10 10 0
s s s s ms ms us
10 15 1.7 -0.1 18 5.0 +0.4
ms V V V
Vta2
-25
+25
mV
Vtr
-25
+25
mV
Vtv
-25
+25
mV
VTRIP Programming parameters are periodically sampled and are not 100% Tested.
14
X5001
Vcc Supply Current vs. Temperature (ISB)
Watchdog Timer On (Vcc = 5V) 17 14 Isb (uA) 11 20 18
tWDO vs. Voltage/Temperature (WD1,0=1,1)
1.85 1.80 1.75 Reset (seconds) 1.70 1.65 1.60 1.55 1.50 1.45 1.40 90C 1.7 3.1 Voltage 4.5 90C 25C -40C
15 Watchdog Timer On (Vcc = 3V)
Watchdog Timer Off (Vcc = 3V, 5V) 0.55 0.35 -40C 25C Temp (c)
1.0
VTRIP vs. Temperature (programmed at 25C)
5.025 5.000 4.975 3.525 Voltage 3.500 3.475 2.525 2.500 2.475 0 25 Temperature 85 Vtrip=2.5V Vtrip=3.5V Vtrip=5V
tWDO vs. Voltage/Temperature (WD1,0=1,0)
0.85 0.80 Reset (seconds) -40C 0.75 25C 0.70 0.65 0.60 1.7 90C
3.1 Voltage
4.5
tPURST vs. Temperature
280 275 270 265 Time (ms) 260 255 250 245 240 235 -40 25 Degrees C 90
tWDO vs. Voltage/Temperature (WD1,0 0=0,1)
0.30 0.29 0.28 0.27 0.26 0.25 0.24 0.23 0.22 0.21 0.20 1.7
Reset (seconds)
25C
-40C
90C
3.1 Voltage
4.5
15
X5001
8-LEAD PLASTIC SMALL OUTLINE GULL WING PACKAGE TYPE S
0.150 (3.80) 0.158 (4.00) PIN 1 INDEX
0.228 (5.80) 0.244 (6.20)
PIN 1
0.014 (0.35) 0.019 (0.49)
0.188 (4.78) 0.197 (5.00)
(4X) 7
0.053 (1.35) 0.069 (1.75)
0.050 (1.27)
0.004 (0.19) 0.010 (0.25)
0.010 (0.25) 0.020 (0.50) X 45
0.050" TYPICAL
0- 8 0.0075 (0.19) 0.010 (0.25) 0.016 (0.410) 0.037 (0.937) 0.250"
0.050" TYPICAL
FOOTPRINT
0.030" TYPICAL 8 PLACES
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
16
X5001
8-LEAD PLASTIC, TSSOP PACKAGE TYPE V ,
.025 (.65) BSC
.169 (4.3) .252 (6.4) BSC .177 (4.5)
.114 (2.9) .122 (3.1)
.047 (1.20)
.0075 (.19) .0118 (.30)
.002 (.05) .006 (.15)
.010 (.25) Gage Plane 0- 8 .019 (.50) .029 (.75) Detail A (20X) Seating Plane
.031 (.80) .041 (1.05)
See Detail "A"
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
17
X5001
Ordering Information
Vcc Range Vtrip Range Package Operating Temperature Range PART NUMBER RESET (Active LOW)
8 pin PDIP 4.5-5.5V 4.5.4.75 8L SOIC 8L TSSOP 8 pin PDIP 4.5-5.5V 4.25.4.5 8L SOIC 8L TSSOP 2.7-5.5V 2.7-5.5V 2.85-3.0 2.55-2.7 8L TSSOP 8L SOIC 8L SOIC
0oC - 70oC 0oC - 70oC 0oC - 70oC 0oC - 70oC 0oC - 70oC 0oC - 70oC 0oC - 70oC 0oC - 70oC 0oC 70oC
X5001P-4.5A X5001S8-4.5A X5001V8-4.5A X5001P X5001S8 X5001V8 X5001S8-2.7A X5001S8-2.7 X5001V8-2.7
18
X5001
Part Mark Information 8-Lead TSSOP YWW XXXXX 501AG = 1.8 to 3.6V, 0 to +70C, VTRIP=1.7-1.8V 501AH = 1.8 to 3.6V, -40 to +85C, VTRIP=1.7-1.8V 501F = 2.7 to 5.5V, 0 to +70C, VTRIP=2.55-2.7V 501G = 2.7 to 5.5V, -40 to +85C, VTRIP=2.55-2.7V 501AN = 2.7 to 5.5V, 0 to +70C, VTRIP=2.85-3.0V 501AP = 2.7 to 5.5V, -40 to +85C, VTRIP=2.85-3.0V 501 = 4.5 to 5.5V, 0 to +70C, VTRIP=4.25-4.5V 501I = 4.5 to 5.5V, -40 to +85C, VTRIP=4.25-4.5V 501AL = 4.5 to 5.5V, 0 to +70C, VTRIP=4.5-4.75V 501AM = 4.5 to 5.5V, -40 to +85C, VTRIP=4.5-4.75V 8-Lead SOIC X5001 YWW XX AG = 1.8 to 3.6V, 0 to +70C, VTRIP=1.7-1.8V AH = 1.8 to 3.6V, -40 to +85C, VTRIP=1.7-1.8V F = 2.7 to 5.5V, 0 to +70C, VTRIP=2.55-2.7V G = 2.7 to 5.5V, -40 to +85C, VTRIP=2.55-2.7V AN = 2.7 to 5.5V, 0 to +70C, VTRIP=2.85-3.0V AP = 2.7 to 5.5V, -40 to +85C, VTRIP=2.85-3.0V Blank = 4.5 to 5.5V, 0 to +70C, VTRIP=4.25-4.5V I = 4.5 to 5.5V, -40 to +85C, VTRIP=4.25-4.5V AL = 4.5 to 5.5V, 0 to +70C, VTRIP=4.5-4.75V AM = 4.5 to 5.5V, -40 to +85C, VTRIP=4.5-4.75V
YWW = year/work week device is packaged.
LIMITED WARRANTY Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and prices at any time and without notice. Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, licenses are implied. U.S. PATENTS Xicor products are covered by one or more of the following U.S. Patents: 4,263,664; 4,274,012; 4,300,212; 4,314,265; 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829, 482; 4,874, 967; 4,883, 976. Foreign patents and additional patents pending. LIFE RELATED POLICY In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection and correction, redundancy and back-up features to prevent such an occurence. Xicor's products are not authorized for use in critical components in life support devices or systems. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 19

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